C7.8 External Debug AArch32 Processor Feature Register

The EDAA32PFR characteristics are:

Purpose

Provides additional information about implemented PE features in AArch32.

Usage constraints

This register is accessible as follows:

Default
RO
Configurations
EDAA32PFR is in the Debug power domain.
Attributes

EDAA32PFR is a 64-bit register.

Figure C7-7 EDAA32PFR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[63:16]

Reserved, res0.

AA32EL3, [15:12]

AArch32 EL3 Exception level handling.

0001EL3 can be executed in AArch32 Execution State only.

All other values are reserved.

AA32EL2, [11:8]

AArch32 EL2 Exception level handling.

0001EL2 can be executed in AArch32 Execution State only.

All other values are reserved.

PMSA, [7:4]

Indicates support for an ARMv8-R PMSA.

In ARMv8-A, the only permitted value is 0x0.

VMSA, [7:4]

Indicates support for an ARMv8-R PMSA.

In ARMv8-A, the only permitted value is 0x0.

The EDAA32PFR [31:0] can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xD60.

The EDAA32PFR [63:32] can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xD64.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.