A10.2 CHI configurations

This section describes the CHI configurations.

The following table shows the permitted combinations of these signals and the supported configurations in the Cortex®‑A32 processor, with a CHI bus.

Table A10-1 Supported CHI configurations

Signal Feature
CHI non-coherent CHI outer coherent CHI inner coherent

No L3 cache

With L3 cache

No L3 cache

With L3 cache

No L3 cache

With L3 cache

BROADCASTCACHEMAINT 0 1 0 1 0 1
BROADCASTOUTER 0 0 1 1 1 1
BROADCASTINNER 0 0 0 0 1 1

The following table shows the key features in each of the supported CHI configurations.

Table A10-2 Supported features in the CHI configurations

Features Configuration
CHI non-coherent, no L3 cache CHI non-coherent, with L3 cache CHI outer coherent CHI inner coherent
Cache maintenance requests on TXREQ channel No Yes Yes Yes
Snoops on RXREQ channel No No Yes Yes
Coherent requests on TXREQ channel No No Yes Yes
DVM requests on TXREQ channel No No No Yes
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