C7.7 External Debug Feature Register

The EDDFR characteristics are:

Purpose
Provides top level information about the debug system in AArch64.
Usage constraints

This register is accessible as follows:

Default

RO
Configurations

EDDFR is in the Debug power domain.

Attributes
EDDFR is a 64-bit register.
Figure C7-6 EDDFR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[63:32]

Reserved, res0.

CTX_CMPs, [31:28]

Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.

[27:24]

Reserved, res0.

WRPs, [23:20]

Number of watchpoints, minus 1. The value of 0b0000 is reserved.

[19:16]

Reserved, res0.

BRPs, [15:12]

Number of breakpoints, minus 1. The value of 0b0000 is reserved.

PMUVer, [11:8]

Performance Monitors extension version. Indicates whether system register interface to Performance Monitors extension is implemented. Defined values are:

0x0000Performance Monitors extension system registers not implemented.
0x0001Performance Monitors extension system registers implemented, PMUv3.
0x11111Implementation defined form of performance monitors supported, PMUv3 not supported.

All other values are reserved.

TraceVer [7:4]

Trace support. Indicates whether system register interface to a trace macrocell is implemented. Defined values are:

0x0000Trace macrocell system registers not implemented.
0x0001Trace macrocell system registers implemented.

All other values are reserved.

A value of 0x0000 only indicates that no system register interface to a trace macrocell is implemented. A trace macrocell might nevertheless be implemented without a system register interface.

UNKOWN, [7:4]

Reserved, unknown.

EDDFR[31:0] can be accessed through the external debug interface, offset 0xD28.

EDDFR[63:32] can be accessed through the external debug interface, offset 0xD2C.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.