Using this book

This book is organized into the following chapters:

Part A Functional Description

This part describes the main functionality of the Cortex®‑A32 processor.

Chapter A1 Introduction

This chapter provides an overview of the Cortex®‑A32 processor and its features.

Chapter A2 Technical Overview

This chapter describes the structure of the Cortex®‑A32 processor.

Chapter A3 Clocks, Resets, and Input Synchronization

This chapter describes the clocks of the Cortex®‑A32 processor. It also describes the reset options.

Chapter A4 Power Management

This chapter describes the power domains and the power modes in the Cortex®‑A32 processor.

Chapter A5 Cache Behavior and Cache Protection

This chapter describes the CPU and SCU cache protection features of the Cortex®‑A32 processor.

Chapter A6 L1 Memory System

This chapter describes the L1 instruction cache and data cache.

Chapter A7 L2 Memory System

This chapter describes the L2 memory system and the Snoop Control Unit (SCU) that is tightly integrated with it.

Chapter A8 AXI Master Interface

This chapter describes the AXI master memory interface.

Chapter A9 ACE Master Interface

This chapter describes the ACE master interface.

Chapter A10 CHI Master Interface

This chapter describes the CHI master memory interface.

Chapter A11 ACP Slave Interface

This chapter describes the ACP slave interface.

Chapter A12 GIC CPU Interface

This chapter describes the Generic Interrupt Controller (GIC) CPU interface of the processor.

Part B Register Descriptions

This part describes the non-debug registers of the Cortex®‑A32 processor.

Chapter B1 AArch32 system registers

This chapter describes the system registers in the AArch32 state.

Chapter B2 GIC registers

This chapter describes the GIC registers.

Chapter B3 Generic Timer registers

This chapter describes the Generic Timer registers.

Part C Debug

This part describes the debug functionality and registers of the Cortex®‑A32 processor.

Chapter C1 Debug

This chapter describes the debug features of the processor.

Chapter C2 PMU

This chapter describes the Performance Monitor Unit (PMU) of the processor.

Chapter C3 ETM

This chapter describes the Embedded Trace Macrocell (ETM) of the processor.

Chapter C4 CTI

This chapter describes the cross-trigger components of the processor.

Chapter C5 Direct access to internal memory

This chapter describes the direct access to internal memory that caches and TLBs use.

Chapter C6 AArch32 debug registers

This chapter describes the debug registers in the AArch32 execution state and shows examples of how to use them.

Chapter C7 Memory-mapped debug registers

This chapter describes the debug memory-mapped registers and shows examples of how to use them.

Chapter C8 ROM table

This chapter describes the ROM table that debuggers can use to determine which components are implemented. It also describes the ROM table registers.

Chapter C9 PMU registers

This chapter describes the PMU registers.

Chapter C10 ETM registers

This chapter describes the ETM registers.

Chapter C11 CTI registers

This chapter describes the CTI registers.

D Appendices

Appendix A Signal Descriptions

This appendix describes the signals at the external interfaces of the processor.

Appendix B AArch32 UNPREDICTABLE Behaviors

The cases in which the Cortex®‑A32 processor implementation diverges from the preferred behavior described in ARMv8 AArch32 unpredictable behaviors.

Appendix C Revisions

This appendix describes the technical changes between released issues of this book.

Glossary

The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.

See the ARM Glossary for more information.

Typographic conventions

italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the ARM glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.

Timing diagrams

The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Figure 1 Key to timing diagram conventions
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Signals

The signal conventions are:

Signal level

The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:

  • HIGH for active-HIGH signals.

  • LOW for active-LOW signals.

Lowercase n

At the start or end of a signal name denotes an active-LOW signal.

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