Part A Functional Description

Table of Contents

A1 Introduction
A1.1 About the Cortex®‑A32 processor
A1.2 Features
A1.3 Implementation options
A1.4 Supported standards and specifications
A1.5 Test features
A1.6 Design tasks
A1.7 Product revisions
A2 Technical Overview
A2.1 Components
A2.2 Interfaces
A2.3 About system control
A2.4 About the Generic Timer
A2.5 About the memory model
A3 Clocks, Resets, and Input Synchronization
A3.1 Clocks
A3.2 Input synchronization
A3.3 Resets
A4 Power Management
A4.1 Power domains
A4.2 Power modes
A4.3 Core Wait for Interrupt
A4.4 Core Wait for Event
A4.5 L2 Wait for Interrupt
A4.6 Powering down an individual core
A4.7 Powering up an individual core
A4.8 Powering down the processor without system driven L2 flush
A4.9 Powering up the processor without system driven L2 flush
A4.10 Powering down the processor with system driven L2 flush
A4.11 Powering up the processor with system driven L2 flush
A4.12 Entering Dormant mode
A4.13 Exiting Dormant mode
A4.14 Event communication using WFE or SEV
A4.15 Communication to the Power Management Controller
A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 signals
A4.17 Q-channel
A5 Cache Behavior and Cache Protection
A5.1 Cached memory types
A5.2 Coherency between data caches with the MOESI protocol
A5.3 Cache misses, unexpected cache hits, and speculative fetches
A5.4 Disabling a cache
A5.5 Invalidating or cleaning a cache
A5.6 About read allocate mode
A5.7 About cache protection
A5.8 Error reporting
A5.9 Error injection
A6 L1 Memory System
A6.1 About the L1 memory system
A6.2 TLB Organization
A6.3 Program flow prediction
A6.4 About the internal exclusive monitor
A6.5 About data prefetching
A7 L2 Memory System
A7.1 About the L2 memory system
A7.2 Snoop and maintenance requests
A7.3 Support for memory types
A7.4 Memory type information exported from the processor
A7.5 Handling of external aborts
A8 AXI Master Interface
A8.1 About the AXI master interface
A8.2 AXI privilege information
A8.3 AXI transactions
A8.4 Attributes of the AXI master interface
A9 ACE Master Interface
A9.1 About the ACE master interface
A9.2 ACE configurations
A9.3 ACE privilege information
A9.4 ACE transactions
A9.5 Attributes of the ACE master interface
A9.6 Snoop channel properties
A9.7 AXI compatibility mode
A10 CHI Master Interface
A10.1 About the CHI master interface
A10.2 CHI configurations
A10.3 Attributes of the CHI master interface
A10.4 CHI channel properties
A10.5 CHI transactions
A11 ACP Slave Interface
A11.1 About the ACP
A11.2 Transfer size support
A11.3 ACP performance
A11.4 ACP user signals
A12 GIC CPU Interface
A12.1 Bypassing the GIC CPU Interface
A12.2 Memory map for the GIC CPU interface
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