Part B Register Descriptions

Table of Contents

B1 AArch32 system registers
B1.1 AArch32 register summary
B1.2 c0 registers
B1.3 c1 registers
B1.4 c2 registers
B1.5 c3 registers
B1.6 c4 registers
B1.7 c5 registers
B1.8 c6 registers
B1.9 c7 registers
B1.10 c7 system operations
B1.11 c8 system operations
B1.12 c9 registers
B1.13 c10 registers
B1.14 c11 registers
B1.15 c12 registers
B1.16 c13 registers
B1.17 c14 registers
B1.18 c15 registers
B1.19 64-bit registers
B1.20 AArch32 Identification registers
B1.21 AArch32 Virtual memory control registers
B1.22 AArch32 Fault handling registers
B1.23 AArch32 Other System control registers
B1.24 AArch32 Address registers
B1.25 AArch32 Thread registers
B1.26 AArch32 Performance monitor registers
B1.27 AArch32 Secure registers
B1.28 AArch32 Virtualization registers
B1.29 AArch32 GIC system registers
B1.30 AArch32 Generic Timer registers
B1.31 AArch32 Implementation defined registers
B1.32 Auxiliary Control Register
B1.33 Auxiliary Data Fault Status Register
B1.34 Auxiliary ID Register
B1.35 Auxiliary Instruction Fault Status Register
B1.36 Auxiliary Memory Attribute Indirection Register 0
B1.37 Auxiliary Memory Attribute Indirection Register 1
B1.38 Configuration Base Address Register
B1.39 Cache Size ID Register
B1.40 Cache Level ID Register
B1.41 Architectural Feature Access Control Register
B1.42 CPU Auxiliary Control Register
B1.43 CPU Extended Control Register
B1.44 CPU Memory Error Syndrome Register
B1.45 Cache Size Selection Register
B1.46 Cache Type Register
B1.47 Domain Access Control Register
B1.48 Data Fault Address Register
B1.49 Data Fault Status Register
B1.50 DFSR with Short-descriptor translation table format
B1.51 DFSR with Long-descriptor translation table format
B1.52 Encoding of ISS[24:20] when HSR[31:30] is 0b00
B1.53 FCSE Process ID Register
B1.54 Hyp Auxiliary Configuration Register
B1.55 Hyp Auxiliary Control Register
B1.56 Hyp Auxiliary Data Fault Status Syndrome Register
B1.57 Hyp Auxiliary Instruction Fault Status Syndrome Register
B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0
B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1
B1.60 Hyp Architectural Feature Trap Register
B1.61 Hyp Configuration Register
B1.62 Hyp Configuration Register 2
B1.63 Hyp Debug Control Register
B1.64 Hyp Data Fault Address Register
B1.65 Hyp Instruction Fault Address Register
B1.66 Hyp IPA Fault Address Register
B1.67 Hyp System Control Register
B1.68 Hyp Syndrome Register
B1.69 Hyp System Trap Register
B1.70 Hyp Translation Control Register
B1.71 Hyp Vector Base Address Register
B1.72 Auxiliary Feature Register 0
B1.73 Debug Feature Register 0
B1.74 Instruction Set Attribute Register 0
B1.75 Instruction Set Attribute Register 1
B1.76 Instruction Set Attribute Register 2
B1.77 Instruction Set Attribute Register 3
B1.78 Instruction Set Attribute Register 4
B1.79 Instruction Set Attribute Register 5
B1.80 Memory Model Feature Register 0
B1.81 Memory Model Feature Register 1
B1.82 Memory Model Feature Register 2
B1.83 Memory Model Feature Register 3
B1.84 Processor Feature Register 0
B1.85 Processor Feature Register 1
B1.86 Instruction Fault Address Register
B1.87 Instruction Fault Status Register
B1.88 IFSR with Short-descriptor translation table format
B1.89 IFSR with Long-descriptor translation table format
B1.90 Interrupt Status Register
B1.91 L2 Auxiliary Control Register
B1.92 L2 Control Register
B1.93 L2 Extended Control Register
B1.94 L2 Memory Error Syndrome Register
B1.95 Memory Attribute Indirection Registers 0 and 1
B1.96 Main ID Register
B1.97 Multiprocessor Affinity Register
B1.98 Non-Secure Access Control Register
B1.99 Normal Memory Remap Register
B1.100 Physical Address Register
B1.101 Primary Region Remap Register
B1.102 Revision ID Register
B1.103 Reset Management Register
B1.104 Secure Configuration Register
B1.105 System Control Register
B1.106 Secure Debug Control Register
B1.107 Secure Debug Enable Register
B1.108 TCM Type Register
B1.109 TLB Type Register
B1.110 Translation Table Base Control Register
B1.111 TTBCR with Short-descriptor translation table format
B1.112 TTBCR with Long-descriptor translation table format
B1.113 Translation Table Base Register 0
B1.114 TTBR0 with Short-descriptor translation table format
B1.115 TTBR0 with Long-descriptor translation table format
B1.116 Translation Table Base Register 1
B1.117 TTBR1 with Short-descriptor translation table format
B1.118 TTBR1 with Long-descriptor translation table format
B1.119 Vector Base Address Register
B1.120 Virtualization Multiprocessor ID Register
B1.121 Virtualization Processor ID Register
B1.122 Virtualization Translation Control Register
B2 GIC registers
B2.1 CPU interface register summary
B2.2 Active Priority Register
B2.3 CPU Interface Identification Register
B2.4 Virtual interface control register summary
B2.5 VGIC Type Register
B2.6 Virtual CPU interface register summary
B2.7 VM Active Priority Register
B2.8 VM CPU Interface Identification Register
B3 Generic Timer registers
B3.1 AArch32 Generic Timer register summary
Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.