A1.3 Implementation options

The Cortex®‑A32 processor is highly configurable. Build-time configuration options make it possible to meet functional requirements with the smallest possible area and power. In a configuration with more than one core, all cores have the same build-time configuration.

The following table lists the implementation options for a core.

Table A1-1 Implementation options for a core

Feature Range of options Notes
L1 instruction cache size
  • 8K
  • 16K
  • 32K
  • 64K
 
L1 data cache size
  • 8K
  • 16K
  • 32K
  • 64K
 
CPU cache protection
  • Included
  • Not included
  • Not available if the L2 cache is implemented without SCU-L2 cache protection.
  • Also protects the L1 duplicate tags in the SCU.
GIC CPU interface
  • Included
  • Not included
 
ETM
  • Included
  • Not included
 
Advanced SIMD and floating-point support
  • Included
  • Not included
 
Cryptographic Extension
  • Included
  • Not included
There is no option to implement the Cryptographic Extension without the Advanced SIMD and floating-point support.

The following table lists the implementation options at build time for the processor.

Table A1-2 Implementation options for the processor

Feature Range of options Notes
Number of cores
  • 1
  • 2
  • 3
  • 4
All cores have the same build-time configuration.
Main bus interface
  • AMBA 4 AXI
  • AMBA 4 ACE
  • AMBA 5 CHI
 
L2 cache
  • Included
  • Not included
If it is present, all cores share one L2 cache.
L2 cache size
  • 128K
  • 256K
  • 512K
  • 1024K
 
L2 data RAM input latency
  • 1 cycle
  • 2 cycles
 
L2 data RAM output latency
  • 2 cycles
  • 3 cycles
 
SCU-L2 cache protection
  • Included
  • Not included
Protects the L2 tag and L2 data RAMs with ECC.
Accelerator Coherency Port (ACP)
  • Included
  • Not included
Part of the SCU-L2. If the processor does not include an L2 cache, it cannot implement the ACP.
Debug memory map
  • v8 debug memory map
  • v7 debug memory map
 
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