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The Cortex®‑A32 processor has several interfaces to connect it to a SoC.
Table A2-1 Cortex‑A32 interfaces
|PMU events||Performance events provide useful information on the operation of the processor that you can use for debug and code profiling. A subset of available performance events is exported on the PMU event bus.|
Outputs trace information for debugging. The ATB interface is compatible with the CoreSight architecture.
|Memory||AXI, ACE, or CHI||ACE can also be used with AXI peripherals.|
This slave interface reduces software cache maintenance operations when the cores share memory regions with other masters and allows other masters to allocate data into the L2 cache. It allows an external master to make coherent requests to shared memory, but it does not support cache maintenance, coherency, barrier, or DVM transactions.
|Debug||APB||Allows access to debug registers and resources, for example, to set watchpoints and breakpoints.|
|Cross-trigger||CTI||This external interface is connected to the CoreSight CTI corresponding to each core through a simplified CTM.|
|Design for Test (DFT)||Allows an industry standard Automatic Test Pattern Generation (ATPG) tool to test logic.|
|Memory Built-In Self Test (MBIST)||Provides support for manufacturing test of the memories embedded in the Cortex‑A32 processor.|
|Power management||Q-channel||Enables communication to an external power controller.|