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The processor optionally implements the GIC CPU Interface. If present, you can disable it by asserting the GICCDISABLE signal HIGH at reset.
If the GIC is enabled, the input pins nVIRQ and nVFIQ must be tied off to HIGH because the internal GIC CPU interface generates the virtual interrupt signals to the cores. Software controls the nIRQ and nFIQ signals, therefore there is no requirement to tie them HIGH. If you disable the GIC CPU interface, a GIC that is external to the processor can drive the input signals nVIRQ and nVFIQ.
Asserting the GICCDISABLE signal HIGH at reset removes access to the memory-mapped and system GIC CPU Interface registers.