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The Generic Timer can schedule events and trigger interrupts that are based on an incrementing counter value. It generates timer events as active-LOW interrupt outputs and event streams.
The Cortex®‑A32 processor does not include the system counter. This resides in the SoC. The system counter value is distributed to the Cortex‑A32 processor with a synchronous binary encoded 64-bit bus, CNTVALUEB[63:0].
Because CNTVALUEB[63:0] is generated from a system counter that typically operates at a slower frequency than the processor clock, CLKIN, the CNTCLKEN input is provided. CNTCLKEN is registered inside the processor and then used as a clock enable for CNTVALUEB[63:0]. This allows a multicycle path to be applied to the CNTVALUEB[63:0]. The following figure shows the interface.
The value on CNTVALUEB[63:0] is required to be stable whenever the internally registered version of the CNTCLKEN clock enable is asserted. CNTCLKEN must be synchronous and balanced with respect to CLKIN and must toggle at integer ratios of the processor CLKIN.