A3.2 Input synchronization

The Cortex®‑A32 processor synchronizes certain input signals. The SoC can present these inputs asynchronously. All other external signals must be synchronous with reference to CLKIN.

Input signals that the Cortex‑A32 processor synchronizes:

  • nCORERESET.
  • nCPUPORESET.
  • nFIQ.
  • nIRQ.
  • nL2RESET.
  • nMBISTRESET.
  • nPRESETDBG.
  • nREI.
  • nSEI.
  • nVFIQ.
  • nVIRQ.
  • nVSEI.
  • CLREXMONREQ.
  • CPUQREQn.
  • CTICHOUTACK.
  • CTIIRQACK.
  • DBGEN.
  • EDBGRQ.
  • EVENTI.
  • L2FLUSHREQ.
  • L2QREQn.
  • NEONQREQn.
  • NIDEN.
  • SPIDEN.
  • SPNIDEN.

Input signals that the Cortex‑A32 processor synchronizes under certain conditions:

  • CTICHIN.

The synchronized CTICHIN input signals are used only if the CISBYPASS input signal is deasserted LOW. If the CISBYPASS signal is asserted HIGH the CTICHIN synchronizers are not used, and the SoC must present the CTICHIN synchronously to CLKIN.

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