A3.3 Resets

The Cortex®‑A32 processor has active-LOW reset input signals that can be asynchronously asserted HIGH to LOW, or deasserted LOW to HIGH.

nCPUPORESET[CN:0]

Where CN is the number of cores minus one.

Power On reset signals. These primary, cold reset signals initialize all resettable registers in the corresponding core, including debug registers and ETM registers.

nCORERESET[CN:0]
These primary reset signals initialize all resettable registers in the corresponding core, not including debug registers and ETM registers.
nPRESETDBG
This single, processor-wide signal resets the integrated CoreSight components that connect to the external PCLK domain, such as debug logic.
nL2RESET
This single, processor-wide signal resets all resettable registers in the L2 memory system and the logic in the SCU or mini-SCU.
nMBISTRESET
An external MBIST controller can use this signal to reset the entire SoC. The nMBISTRESET signal resets all resettable registers in the cluster, for entry into, and exit from, MBIST mode.

Reset synchronization logic inside the processor ensures that reset deassertion is synchronous for all resettable registers. The processor clock is not required for reset assertion, but it must be present for reset deassertion to ensure reset synchronization.

In general, the reset time only requires three processor clock cycles.

Note:

The application of a retention state can affect how long reset assertion is required. You must hold the reset signal active-LOW until the power returns and the unit or processor is ready for the reset to take effect if:
  • The Advanced SIMD and floating-point unit of a core undergoing a reset is in retention state.
  • A core that is being reset is in retention state.

The time that is taken for retention exit and the behavior of the power controller varies by partner and by implementation.

The following table describes the valid reset signal combinations. All other combinations of reset signals are illegal. In the table, n designates the core that is reset.

Table A3-1 Valid reset combinations

Reset combination Signals Value Description
Cluster cold reset

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 0

all = X

0

0

1

All logic is held in reset.

nCORERESET can be asserted, but is not required.

Cluster cold reset with debug active

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 0

all = X

1

0

1

All cores are held in reset so they can be powered up. The L2 is held in reset, but must remain powered up. This enables external debug over power down for the cluster.

nCORERESET can be asserted, but is not required.

Individual core cold reset with debug active

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

[n] = 0

[n] = X

1

1

1

Individual core is held in reset, so that the core can be powered up. This enables external debug over power down for the core that is held in reset.

nCORERESET can be asserted, but is not required.

Individual core warm reset with trace and debug active

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

[n] = 1

[n] = 0

1

1

1

Individual core is held in reset.
Debug logic reset

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 1

all = 1

0

1

1

Cluster debug logic is held in reset.
MBIST reset

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 1

all = 1

1

1

0

All logic is held in reset.
Normal state

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 1

all = 1

1

1

1

No logic is held in reset.
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