A4.1 Power domains

A core or a processor can support different power domains. Each power domain has valid and accepted power states.

The Cortex®‑A32 processor provides mechanisms and support to control both dynamic and static power dissipation. The individual cores in the Cortex‑A32 processor support four main levels of power management which correspond to the power domains shown in the following table:

Table A4-1 Power domain description

Power domain Description
PDMINERVA

Includes the SCU, the optional L2 cache control logic, and debug registers that are described as being in the debug domain.

PDL2 Includes the L2 data RAM, L2 tag RAM, L2 victim RAM, and the SCU duplicate tag RAM.
PDCPU<n>

Includes the optional Advanced SIMD and floating-point support, the L1 cache and TLB RAMs, and the debug registers that are described as being in the processor domain.

n is 0, 1, 2, or 3. It represents core 0, core 1, core 2, or core 3. If a core is not present, the corresponding power domain is not present.

PDCPUADVSIMD<n>

Represents the Advanced SIMD and floating-point block of core n.

n is 0, 1, 2, or 3. It represents core 0, core 1, core 2, or core 3. If a core is not present, the corresponding power domain is not present.

The separate PDMINERVA and PDL2 power domains can remain active even when all the cores are powered down. It means that the processor can continue to accept snoops from external devices to access the L2 cache.

The following figure shows an example of the domains embedded in a System-on-Chip (SoC) power domain.

Figure A4-1 Power domains
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The power domains can be controlled independently to give different combinations of powered-up and powered-down domains. However, only some powered-up and powered-down domain combinations are valid and supported.

Table A4-2 Power state description

Power state Description
Off Block is power gated
Ret Logic or RAM retention power only
On Block is active

The following tables show the supported power domain states for the processor.

CAUTION:

States that are not shown in the tables are unsupported and must not occur.

Table A4-3 Supported processor power states

Power domains Description
PDMINERVA PDL2 PDCPU<n>
Off Off Off Processor off.
Off On/Ret Off L2 cache dormant mode.
On Ret See Table A4-4 Supported core power states

Processor on, L2 RAMs retained.

All cores either off or in WFx.

This is an L2 RAM retention entry or residency condition.

On Ret See Table A4-4 Supported core power states

Processor on, L2 RAMs retained.

At least one core running.

This is a transient condition.

On On See Table A4-4 Supported core power states Processor on, SCU/L2 RAMs active.

The following table describes the supported power domain states for individual cores. The power domain state in each core is independent of all other cores.

Table A4-4 Supported core power states

Power domains Description
PDCPU PDADVSIMD
Off Off Core off.
On On Core on. Advanced SIMD and floating-point on.
On Ret AdvSIMD retention. Advanced SIMD and floating-point in retention.
Ret Ret Core retention. Core logic and Advanced SIMD and floating-point in retention.

You must follow the dynamic power management and powerup and powerdown sequences described in the following sections. Any deviation from these sequences can lead to unpredictable results.

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