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The processor supports the following power modes:
When a Cortex‑A32 core is in standby mode, it is architecturally clock gated at the top of the clock tree. Each core in the cluster can be put in standby mode separately from the other cores, by executing a Wait for Interrupt (WFI) or Wait for Event (WFE) instruction.
The PDCPU power domain for an individual core is shut down and the state held in this domain is lost.
All the cores and L2 control logic are powered down while the L2 cache RAMs are powered up and retain state. The RAM blocks that remain powered up during Dormant mode are:
Contact ARM for information about retention state.