A4.3 Core Wait for Interrupt

Programmers can use the Wait for Interrupt (WFI) instruction to cause the core to enter a low-power state.

Wait for Interrupt is a feature of the ARMv8-A architecture that puts the core in a low-power state by disabling most of the clocks in the core while keeping the core powered up. Apart from a small dynamic power overhead on the logic to enable the core to wake up from WFI low-power state, this reduces the power drawn to static leakage current only.

When executing the WFI instruction, the core waits for all instructions in the core to retire before entering the idle or low power state. The WFI instruction ensures that all explicit memory accesses that occurred before the WFI instruction in program order have retired. For example, the WFI instruction ensures that the following instructions received the required data or responses from the L2 memory system:

In addition, the WFI instruction ensures that store instructions have updated the cache or have been issued to the SCU.

While the core is in WFI low-power state, the clocks in the core are temporarily enabled without causing the core to exit WFI low-power state, when any of the following events are detected:

Exit from WFI low-power state occurs when the core detects a reset or one of the WFI wake up events as described in the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

On entry into WFI low-power state, STANDBYWFI for that core is asserted. Assertion of STANDBYWFI guarantees that the core is in idle and low-power state. STANDBYWFI continues to assert even if the clocks in the core are temporarily enabled because of an L2 snoop request, cache or TLB maintenance operation, or an APB access.

STANDBYWFI does not indicate completion of L2 memory system transactions initiated by the processor. All Cortex®‑A32 processor implementations contain an L2 memory system. This includes implementations without an L2 cache.

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