A4.5 L2 Wait for Interrupt

When all the cores are in WFI low-power state, the shared L2 memory system logic that is common to all the cores can also enter a WFI low-power state.

Entry into L2 WFI low-power state can occur only if specific requirements are met and the following sequence applied:

When the L2 memory system completes the outstanding transactions for AXI, ACE, or CHI interfaces, it can then enter the L2 WFI low-power state. On entry into L2 WFI low-power state, STANDBYWFIL2 is asserted. Assertion of STANDBYWFIL2 guarantees that the L2 memory system is idle and does not accept new transactions.

Exit from L2 WFI low-power state occurs on one of the following events:

When a core exits permanently from WFI low-power state, STANDBYWFI for that core is deasserted. When the L2 memory system logic exits from WFI low-power state, STANDBYWFIL2 is deasserted. The SoC must continue to assert ACINACTM or SINACT until STANDBYWFIL2 has deasserted.

The following figure shows the L2 WFI timing for a 4-core configuration.

Figure A4-3 L2 Wait For Interrupt timing
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