A4.6 Powering down
an individual core
To enable a core to be powered down, the implementation must place the core on a separately controlled power supply. In addition, you must clamp the outputs of the core to benign values while the entire cluster is powered down.
To power down the core, apply the following sequence:
Disable the data cache,
by clearing the SCTLR.C bit, or the HSCTLR.C bit if in Hyp mode.
This prevents more data cache allocations and causes cacheable memory
attributes to change to Normal Non-cacheable. Subsequent loads and
stores do not access the L1 or L2 caches.
Clean and invalidate all data from the L1 Data cache. The SCU duplicate tag
RAMs for this core are now empty. This prevents any new data cache snoops or data cache
maintenance operations from other cores in the cluster being issued to this core.
Disable data coherency with other
cores in the cluster, by clearing the CPUECTLR.SMPEN bit. Clearing
the SMPEN bit enables the core to be taken out of coherency by preventing
the core from receiving cache or TLB maintenance operations broadcast
by other cores in the cluster.
to ensure that all of the register changes from the previous steps
have been committed.
DSB SY instruction to ensure that
all cache, TLB, and branch predictor maintenance operations issued by any core in the
cluster device before the SMPEN bit was cleared have completed.
WFI instruction and wait until the
STANDBYWFI output is
asserted to indicate that the core is in idle and low-power state.
Deassert DBGPWRDUP LOW.
This prevents any external debug access to the core.
Activate the core output clamps.
Assert nCPUPORESET LOW.
Remove power from the PDCPU power domain.