A4.8 Powering down the processor without system driven L2 flush

When powering down the processor, the PDMINERVA, PDL2, and PDCPU power domains are shut down and all state is lost. In this section, the lead core is defined as the last core to switch off.

To power down the processor, apply the following sequence. For device powerdown, all operations on a lead core must occur after the equivalent step on all non-lead cores.

Procedure

  1. Ensure all non-lead cores are in shutdown mode, see A4.6 Powering down an individual core.
  2. Follow steps 1 and 2 in A4.6 Powering down an individual core.
  3. If the ACP interface is configured, ensure that any master connected to the interface does not send new transactions, then assert AINACTS.
  4. Clean and invalidate all data from the L2 Data cache.
  5. Follow steps 3 to 10 in A4.6 Powering down an individual core.
  6. In an ACE configuration, assert ACINACTM or, in a CHI configuration, assert SINACT. Then, wait until the STANDBYWFIL2 output is asserted to indicate that the L2 memory system is idle. All Cortex®‑A32 processor implementations contain an L2 memory system, including implementations without an L2 cache. This applies to implementations that use the mini-SCU and implementations that use the SCU.
  7. Activate the cluster output clamps.
  8. Remove power from the PDMINERVA and PDL2 power domains.
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