A4.10 Powering down the processor with system driven L2 flush
When powering down the processor, the PDMINERVA, PDL2, and PDCPU power domains are shut down and all state is lost.
To power down the cluster, apply the following sequence:
Ensure all cores are in shutdown mode, see A4.6 Powering down
an individual core.
If the ACP interface is configured, ensure that any master connected to
the interface does not send new transactions, then assert AINACTS. This is necessary to prevent ACP
transactions from allocating new entries in the L2 cache while the hardware cache flush is
Assert L2FLUSHREQ HIGH.
Hold L2FLUSHREQ HIGH until L2FLUSHDONE is asserted.
In an ACE configuration, assert ACINACTM or, in a CHI configuration, assert
SINACT. Then, wait until
the STANDBYWFIL2 output is
asserted to indicate that the L2 memory system is idle. All Cortex®‑A32 processor
implementations contain an L2 memory system, including implementations without an L2
cache. This applies to implementations that use the mini-SCU and implementations that use
Activate the cluster output clamps.
Remove power from the PDMINERVA and PDL2