A4.12 Entering Dormant mode

The processor can enter Dormant mode if certain requirements are met.

To support Dormant mode, you must ensure:

Before entering Dormant mode, the architectural state of the cluster, excluding the contents of the L2 cache RAMs that remain powered up, must be saved to external memory.

To enter Dormant mode, apply the following sequence:


  1. Disable the data cache by clearing the SCTLR.C bit, or the HSCTLR.C bit if in Hyp mode. This prevents more data cache allocations and causes cacheable memory attributes to change to Normal Non-cacheable. Subsequent loads and stores do not access the L1 or L2 caches.
  2. Clean and invalidate all data from the L1 Data cache. The SCU duplicate tag RAM for this core is now empty. This prevents any new data cache snoops or data cache maintenance operations from other cores in the cluster being issued to this core.
  3. Disable data coherency with other cores in the cluster, by clearing the CPUECTLR.SMPEN bit. Clearing the SMPEN bit enables the core to be taken out of coherency by preventing the core from receiving cache or TLB maintenance operations broadcast by other cores in the cluster.
  4. Save architectural state, if required. These state saving operations must ensure that the following occur:

    • All ARM registers, including the CPSR and SPSR, are saved.
    • All system registers are saved.
    • All debug related state is saved.
  5. Execute an ISB instruction to ensure that all of the register changes from the previous steps have been committed.
  6. Execute a DSB instruction to ensure that all cache, TLB, and branch predictor maintenance operations issued by any core in the cluster before the SMPEN bit was cleared have completed. In addition, this ensures that all state saving has completed.
  7. Execute a WFI instruction and wait until the STANDBYWFI output is asserted, to indicate that the core is in idle and low-power state.
  8. Repeat the previous steps for all cores, and wait for all STANDBYWFI outputs to be asserted.
  9. If the ACP interface is configured, ensure that any master connected to the interface does not send new transactions, then assert AINACTS.
  10. If ACE is implemented, the SoC asserts the input pin ACINACTM to idle the AXI master interface after all snoop transactions have been sent on the interface. If CHI is implemented, the SoC asserts the input pin SINACT.

    When the L2 has completed the outstanding transactions for the AXI master and slave interfaces, STANDBYWFIL2 is asserted to indicate that L2 memory system is idle. All Cortex®‑A32 processor implementations contain an L2 memory system, including implementations without an L2 cache.

  11. When STANDBYWFI and STANDBYWFIL2 are asserted for all cores, the cluster is ready to enter Dormant mode. This applies to implementations that use the mini-SCU as well as implementations that use the SCU.
  12. Activate the L2 cache RAM input clamps.
  13. Remove power from the PDCPU and PDMINERVA power domains.
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