- The controller to manage entry to,
and exit from, a device quiescent state. Quiescence management is
typically of, but not restricted to, clock gated, and power gated
retention states, of the device or device partitions.
- The capability to indicate a requirement for exit
from the quiescent state. The associated signaling can contain contributions
from other devices in the same power domain.
- Optional device capability to deny a quiescence request.
- Safe asynchronous interfacing across clock domains.
For more information, see the Low Power Interface
Specification: ARM Q-Channel and P-Channel Interfaces.