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The L1 memory system includes several power-saving and performance-enhancing features. These include separate instruction and data caches, which can be configured independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB.
The MMU provides fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes held in translation tables. These are loaded into the Translation Lookaside Buffer (TLB) when a location is accessed. The key features are:
The L1 instruction-side memory system provides an instruction stream to the DPU. The key features are:
A dedicated instruction cache that:
The L1 data-side memory system responds to load and store requests from the DPU. It also responds to snoop requests that have been forwarded by the SCU from other cores or external masters. The key features are:
A dedicated data cache that: