A6.1 About the L1 memory system

The L1 memory system includes several power-saving and performance-enhancing features. These include separate instruction and data caches, which can be configured independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB.

MMU

The MMU provides fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes held in translation tables. These are loaded into the Translation Lookaside Buffer (TLB) when a location is accessed. The key features are:

  • 10-entry fully-associative instruction micro TLB.
  • 10-entry fully-associative data micro TLB.
  • 2-way set-associative 512-entry unified main TLB.
  • 2-way set-associative 64-entry walk cache.
  • 2-way set-associative 64-entry IPA cache.
L1 instruction-side memory system

The L1 instruction-side memory system provides an instruction stream to the DPU. The key features are:

  • A dedicated instruction cache that:

    • is virtually indexed and physically tagged.
    • is 2-way set associative.
    • is configurable to be 8KB, 16KB, 32KB, or 64KB.
    • uses a cache line length of 64 bytes.
    • uses a pseudo-random replacement policy.
  • A 128-bit read interface to the L2 memory system.
  • Dynamic program flow prediction.
L1 data-side memory system

The L1 data-side memory system responds to load and store requests from the DPU. It also responds to snoop requests that have been forwarded by the SCU from other cores or external masters. The key features are:

  • A dedicated data cache that:

    • is physically indexed and physically tagged.
    • is 4-way set associative.
    • is configurable to be 8KB, 16KB, 32KB, or 64KB.
    • uses a cache line length of 64 bytes.
    • uses a pseudo-random replacement policy.
  • A 128-bit read and 256-bit write interface to the L2 memory system.
  • A 64-bit read and 64-bit write path to the DPU.
  • Read buffers that service the DCU, the IFU, and the TLB.
  • Support for three outstanding data cache misses.
  • Support for eight outstanding linefill requests.
  • A merging store buffer.
  • An internal exclusive monitor.
  • An automatic data prefetch engine.
  • Write stream detection and optimization (read allocate mode).
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