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The processor generates only a subset of all possible ACE transactions on the ACE master interface.
The processor does not generate any FIXED bursts and all WRAP bursts fetch a complete cache line starting with the critical word first. A burst does not cross a cache line boundary.
The cache linefill fetch length is always 64 bytes.
For WriteBack transfers the supported transfers are:
For Non-cacheable transactions:
For Device transactions:
External memory accesses generate the following transactions in an implementation configured with an ACE master interface.
Table A9-4 ACE transactions
|Memory type||Shareability||Domain||Load||Store||Load exclusive||Store exclusive|
ReadNoSnoop and ARLOCKM set to HIGH
WriteNoSnoop and AWLOCKM set to HIGH
|Normal, inner Non-cacheable, outer Non-cacheable||Non-shared||System||ReadNoSnoop||WriteNoSnoop||
ReadNoSnoop and ARLOCKM set to HIGH
|WriteNoSnoop and AWLOCKM set to HIGH|
|Normal, inner Non-cacheable, outer Write-Back or Write-Through, or Normal, inner Write-Through, outer Write-Back, Write-Through or Non-cacheable, or Normal inner Write-Back outer Non-cacheable or Write-Through||Non-shared||System||ReadNoSnoop||WriteNoSnoop||
|Inner-shared||System||ReadNoSnoop||WriteNoSnoop||ReadNoSnoop with ARLOCKM set to HIGH||WriteNoSnoop with ARLOCKM set to HIGH|
|Normal, inner Write-Back, outer Write-Back||Non-shared||Non-shareable||ReadNoSnoop||WriteNoSnoop||
|Inner-shared||Inner Shareable||ReadShared||ReadUnique or CleanUnique if required, then a WriteBack when the line is evicted||ReadShared with ARLOCKM set to HIGH||CleanUnique with ARLOCKM set to HIGH if required, then a WriteBack when the line is evicted|
The following table shows the ACE transactions that can be generated, and some typical operations that might cause the transactions to be generated. This is not an exhaustive list of ways to generate each type of transaction, because there are many possibilities.
Table A9-5 ACE transactions and typical operations
|ReadNoSnoop||Non-cacheable loads or instruction fetches. Linefills of non-shareable cache lines into L1 or L2.|
|ReadOnce||Cacheable loads that are not allocating into the cache, or cacheable instruction fetches when there is no L2 cache.|
|ReadShared||L1 Data linefills started by a load instruction, or L2 linefills started by an instruction fetch.|
|ReadUnique||L1 Data linefills started by a store instruction.|
|CleanUnique||Store instructions that hit in the cache but the line is not in a unique coherence state. Store instructions that are not allocating into the L1 or L2 caches, for example when streaming writes.|
|MakeUnique||Store instructions of a full cache line of data, that miss in the caches, and are allocating into the L2 cache.|
|CleanShared||Cache maintenance instructions.|
|CleanInvalid||Cache maintenance instructions.|
|MakeInvalid||Cache maintenance instructions.|
|DVM||TLB and instruction cache maintenance instructions.|
|DVM complete||DVM sync snoops received from the interconnect.|
|Barriers||DMB and DSB instructions. DVM sync snoops received from the interconnect.|
|WriteNoSnoop||Non-cacheable store instructions. Evictions of non-shareable cache lines from L1 and L2.|
|WriteBack||Evictions of dirty lines from the L1 or L2 cache, or streaming writes that are not allocating into the cache.|
|WriteClean||Evictions of dirty lines from the L2 cache, when the line is still present in an L1 cache. Some cache maintenance instructions.|
|WriteEvict||Evictions of unique clean lines, when configured in the L2ACTLR.|
|Evict||Evictions of clean lines, when configured in the L2ACTLR.|