A6.5 About data prefetching

This section describes the software and hardware data prefetching behavior for the processor.

Preload instructions

PLD instructions look up in the cache and start a linefill if they miss and are to a cacheable address. These instructions retire as soon as their linefill has started, they do not wait for data to be returned. This enables other instructions to execute while the linefill continues in the background.

PLDW instructions are similar to PLD, except that if they miss, the linefill causes data to be invalidated in other cores and masters so that the line is ready for writing.

PLI instructions are treated as NOPs.

Automatic data prefetching and monitoring

The L1 data-side memory system implements an automatic prefetcher that monitors cache misses in the core. When a pattern is detected, the automatic prefetcher starts linefills in the background. The prefetcher recognizes a sequence of data cache misses at a fixed stride pattern that lies in four cache lines, plus or minus. Any intervening stores or loads that hit in the data cache do not interfere with the recognition of the cache miss pattern.

The CPUACTLR enables you to:

  • Deactivate the prefetcher.
  • Alter the sequence length required to trigger the prefetcher.
  • Alter the number of outstanding requests that the prefetcher can make.

Use PLD instructions for data prefetching where short sequences or irregular pattern fetches are required.

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