C5.1 About direct access to internal memory

System registers provide access to the internal memory that the caches and TLBs use. This functionality can be useful when investigating issues where the coherency between the data in the cache and data in system memory is broken.

The appropriate memory block and location are selected using write-only CP15 registers and the data is read from read-only CP15 registers. These operations are available only in EL3. In all other modes, executing the CP15 instruction results in an Undefined Instruction exception.

Table C5-1 AArch32 CP15 registers used to access internal memory

Function Access CP15 operation Rd Data
Data Register 0 Read-only MRC p15, 3, <Rd>, c15, c0, 0 Data
Data Register 1 Read-only MRC p15, 3, <Rd>, c15, c0, 1 Data
Data Register 2 Read-only MRC p15, 3, <Rd>, c15, c0, 2 Data
Data Register 3 Read-only MRC p15, 3, <Rd>, c15, c0, 3 Data
Data Cache Tag Read Operation Register Write-only MCR p15, 3, <Rd>, c15, c2, 0 Set/Way
Instruction Cache Tag Read Operation Register Write-only MCR p15, 3, <Rd>, c15, c2, 1 Set/Way
Data Cache Data Read Operation Register Write-only MCR p15, 3, <Rd>, c15, c4, 0 Set/Way/Offset
Instruction Cache Data Read Operation Register Write-only MCR p15, 3, <Rd>, c15, c4, 1 Set/Way/Offset
TLB Data Read Operation Register Write-only MCR p15, 3, <Rd>, c15, c4, 2 Index/Way
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