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The following table shows the format of the Instruction Cache Tag Read Operation Register and the Instruction Cache Data Read Operation Register.
The set-index range parameter (S) is determined by the following formula:
S = log2(size of the instruction cache in bytes / 2)
Table C5-2 Instruction cache tag and data location encoding
The following table shows the format of the information in Data Register 0 following an Instruction Cache Tag Read Operation.
Table C5-3 Instruction cache tag data format
Valid and set mode:
|||Non-secure state (NS).|
The Instruction Cache Data Read Operation returns two entries from the cache in Data Register 0 and Data Register 1 corresponding to the 16-bit aligned offset in the cache line:
|Data Register 0||Bits[19:0] data from cache offset+
|Data Register 1||Bits[19:0] data from cache offset+
In A32 state these two fields combined always represent a single predecoded instruction. In T32 state, they can represent any combination of 16-bit and partial or full 32-bit instructions.