C5.4 Encoding for the main TLB RAM

The Cortex®‑A32 processor unified TLB is built from a 2-way set-associative RAM based structure. To read the individual entries into the data registers, software must write to the TLB Data Read Operation Register.

The following table shows the format of the TLB Data Read Operation Register.

Table C5-7 Location encoding for the TLB Data Read Operation Register

Bits Description
[31] Unused
[30] TLB way
[29:9] Unused
[8:0]

TLB index

0-255Main TLB RAM
256-287Walk cache RAM
288-319IPA cache RAM
320-511Unused

The TLB Read Data Operation returns the selected entry in Data Register 0-3. The entry uses a 116-bit encoding when parity is enabled and a 113-bit encoding when parity is disabled.

Data Register 0[31:0]TLB Descriptor[31:0].
Data Register 1[31:0]TLB Descriptor[63:32].
Data Register 2[31:0]TLB Descriptor[95:64].
Data Register 3[20:0]TLB Descriptor[115:96].

The following table shows the data fields in the TLB descriptor.

Table C5-8 Main TLB descriptor data fields

Bits Name Description
[115:113] Parity If CPU cache protection is not implemented, these bits are absent.
[112:111] S2 Level

The stage 2 level that gave this translation:

0b00No stage 2 translation performed.
0b01Level 1.
0b10Level 2.
0b11Level 3.
[110:108]

S1 Size

The stage 1 size that gave this translation.

VMSAv8-32 Short-descriptor translation table format:

0b0004KB.
0b01064KB.
0b0111MB.
0b10116MB.
[107:104] Domain

In VMSAv7 format, indicates one of sixteen memory regions.

In non-VMSAv7 formats:

  • Domain[0] stores the contiguous bit information.
  • Domain[1] stores the page size MSB for the combined page size.
  • Domain[2] stores the page size MSB for the stage 1 page size.
[103:96] Memory Type and shareability

See .

[95] XS2 Stage2 executable permissions.
[94] XS1Nonusr Non user mode executable permissions.
[93] XS1Usr User mode executable permissions.
[92-65] PA Physical Address.
[64] NS, descriptor Security state allocated to memory region.
[63:62] HAP Hypervisor access permissions.
[61:59] AP or HYP Access permissions from stage-1 translation, or select EL2 or flag.
[58] nG Not global.
[57:55]

Size

This field shows the encoding for the combined page size for stage 1 and stage 2.

VMSAv8-32 Short-descriptor translation table format:

0b0004KB.
0b01064KB.
0b1001MB.
0b11016MB.
[54:39] ASID Address Space Identifier.
[38:31] VMID Virtual Machine Identifier.
[30] NS (walk) Security state that the entry was fetched in.
[29:2] VA Virtual Address.
[1] Address Sign bit VA[48] sign bit.
[0] Valid

Valid bit:

0Entry does not contain valid data.
1Entry contains valid data.

The following table shows the main TLB memory types and shareability.

Table C5-9 TLB encoding for memory types and shareability

Bits Memory type Description
[7]

Device

Non-coherent, Outer WB

Non-coherent, Outer NC

Non-coherent, Outer WT

0
Coherent, Inner WB and Outer WB 1
[6]

Device

Non-coherent, Outer WB

0

Non-coherent, Outer NC

Non-coherent, Outer WT

1
Coherent, Inner WB and Outer WB

Transience:

0Non-transient
1Transient.
[5:4]

Device

Stage 1 (Non-device) overridden by stage 2 (Device)

00Not overridden
01Overridden.
Non-coherent, Outer WB

Inner type:

10NC.
11WT.
Non-coherent, Outer NC 11
Non-coherent, Outer WT

Inner type:

00NC.
01WB.
10WT.
Coherent, Inner WB and Outer WB

Inner allocation hint:

00NA.
01WA.
10RA.
11WRA.
[3:2] Device

Device type:

00nGnRnE.
01nGnRE.
10nGRE.
11GRE.

Non-coherent, Outer WB

Non-coherent, Outer WT

Coherent, Inner WB and Outer WB

Outer allocation hint:

00NA.
01WA.
10RA.
11WRA.
Non-coherent, Outer NC

Inner type:

00NC.
01WB.
10WT.
11Unused.
[1:0]

Device

Non-coherent, Outer WB

Non-coherent, Outer NC

Non-coherent, Outer WT

Coherent, Inner WB and Outer WB

Shareability:

00Non-shareable.
01Unused.
10Outer shareable.
11Inner shareable.
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