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In most configurations, the L2 memory system consists of an integrated SCU that connects the cores in a cluster, an optional, tightly-coupled L2 cache, and an optional ACP interface. In single core, AXI configurations that do not include CPU cache protection, ACP, or an L2 cache, the SCU is replaced with a more area-efficient mini-SCU.
The same system register control bit enables the L1 data cache and the L2 cache.
The SCU maintains coherency between the L1 and L2 data caches in the processor. It also arbitrates requests for the L2 cache and the AXI, ACE, or CHI master interface.
A coherent request from a core is one that checks for data in the L1 data caches and, if present, the L2 cache. The SCU might send a request to another core to retrieve or invalidate data, or both, depending on the type of coherent request. This request is referred to as a snoop request. If the processor is implemented with an ACE or CHI master interface then the SCU can issue coherent requests on the master interface, which might result in snoop requests being sent to other masters in the system. The SCU might also receive snoop requests from other masters.
The SCU can handle direct cache-to-cache transfers between cores without having to read or write any data to the external memory system. Cache line migration enables dirty cache lines to be moved between cores, and there is no requirement to write back transferred cache line data to the external memory system.
Each core has tag and dirty RAMs that contain the state of the cache line in the L1 data cache. Rather than sending a snoop request to each core to access these for each coherent request, the SCU contains a set of duplicate tags that allows it to check the contents of each L1 data cache. The duplicate tags filter coherent requests so that a snoop request is only sent to a core if the coherent request hits in the corresponding duplicate tags. The duplicate tags are also used to filter snoop requests from the external memory system. This allows the cores and the system to function efficiently even with a high volume of requests.
The SCU does not support hardware management of coherency of the instruction caches. Instruction cache linefills perform coherent reads, however, there is no coherency management of data held in the instruction cache.
Data cache lines are allocated to the L2 cache only when evicted from the L1 memory system, not when first fetched from the system. The only exceptions to this rule are for memory marked with the inner transient hint, or for non-temporal loads that are only ever allocated to the L2 cache. The L1 cache can prefetch data from the system, without data being evicted from the L2 cache.
Instruction cache lines are allocated to the L2 cache when fetched from the system and can be invalidated during maintenance operations.
The L2 cache is 8-way set associative. The L2 cache tags are looked up in parallel with the SCU duplicate tags. If both the L2 tag and SCU duplicate tag hit, a read accesses the L2 cache in preference to snooping one of the other cores.
L2 RAMs are invalidated automatically at reset unless the L2RSTDISABLE signal is set HIGH when the nL2RESET signal is deasserted.
Further features of the L2 cache are:
Configurable size of 128KB, 256KB, 512KB, and 1MB.
The L2 memory system has two abort mechanisms, a synchronous one and an asynchronous one.