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In implementations that include an ACE or CHI master interface, the SCU controls snoop and maintenance requests to the external memory system with the BROADCASTINNER, BROADCASTOUTER, and BROADCASTCACHEMAINT configuration inputs.
Table A7-1 Control pins for snoop and maintenance requests
|BROADCASTINNER||1||The inner shareability domain extends beyond the processor. Inner Shareable snoop and maintenance operations are broadcast externally.|
|0||The inner shareability domain does not extend beyond the processor.|
|BROADCASTOUTER||1||The outer shareability domain extends beyond the processor. Outer shareable snoop and maintenance operations are broadcast externally.|
|0||The outer shareability domain does not extend beyond the processor.|
|BROADCASTCACHEMAINT||1||There are external downstream caches and maintenance operations are broadcast externally.|
|0||There are no downstream caches external to the processor.|
If you set the BROADCASTINNER pin to HIGH you must also set the BROADCASTOUTER pin to HIGH.
In a system that contains a Cortex®‑A32 processor and another processor in a big.LITTLE configuration, you must ensure the BROADCASTINNER and BROADCASTOUTER pins on both processors are set to HIGH so that both processors are in the same Inner Shareable domain.
Cacheable loads and stores to a shareability domain, that does not extend beyond the processor can allocate data to the L1 and L2 caches. However, they do not make coherent requests on the master for these accesses. Instead, they use only ReadNoSnoop or WriteNoSnoop transactions. This always includes non-shareable memory, and might include inner shareable and outer shareable memory, depending on the setting of the BROADCASTINNER and BROADCASTOUTER pins.
If the system sends a snoop to the Cortex‑A32 processor for an address that is present in the L1 or L2 cache, but the line in the cache is in a shareability domain that does not extend beyond the cluster, then the snoop is treated as missing in the cluster.