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The processor generates only a subset of all possible AXI transactions on the AXI master interface.
The processor does not generate any FIXED bursts and all WRAP bursts fetch a complete cache line starting with the critical word first. A burst does not cross a cache line boundary.
The cache linefill fetch length is always 64 bytes.
For WriteBack transfers the supported transfers are:
For Non-cacheable transactions:
For Device transactions:
For translation table walk transactions INCR 1 32-bit, and 64-bit read transfers.
The following points apply to AXI transactions:
External memory accesses generate the following transactions in an implementation configured with an AXI master interface.
Table A8-2 AXI transactions
|Memory type||Shareability||Load||Store||Load exclusive||Store exclusive|
|Device||-||Read||Write||Read with ARLOCKM set HIGH||Write with AWLOCKM set HIGH|
|Normal, inner Non-cacheable, outer Non-cacheable||Non-shared||Read||Write||Read||Write|
|Inner-shared||Read with ARLOCKM set HIGH||Write with ARLOCKM set HIGH|
|Normal, inner Non-cacheable, outer Write-Back or Write-Through, or Normal, inner Write-Through, outer Write-Back, Write-Through or Non-cacheable, or Normal inner Write-Back outer Non-cacheable or Write-Through||Non-shared||Read||Write||Read||Write|
|Inner-shared||Read with ARLOCKM set HIGH||Write with AWLOCKM set HIGH|
|Normal, inner Write-Back, outer Write-Back||Non-shared||Read||Write||Read||Write when the line is evicted|