A9.1 About the ACE master interface

You can configure the processor to use the ACE protocol for the master memory interface.

Read responses

The ACE master can delay accepting a read data channel transfer by holding RREADY LOW for an indeterminate number of cycles. RREADY can be deasserted LOW between read data channel transfers that form part of the same transaction.

The ACE master asserts the read acknowledge signal RACK HIGH in the ACLK cycle following acceptance of the last read data channel transfer for a transaction. RACK is asserted in AXI compatibility mode in addition to ACE configurations.

  • For interoperability of system components, ARM recommends that components interfacing with the ACE master are fully ACE compliant with no reliance on the subset of permitted RACK behavior described for the processor.
  • If the interconnect does not perform hazarding between coherent and non-coherent requests, then, after it has returned the first transfer of read data for a non-coherent read, it must return all the remaining read transfers in the transaction, without requiring progress of any snoops to the cluster that could be to the same address.

Write responses

The ACE master requires that the slave does not return a write response until it has received the write address.

The ACE master always accepts write responses without delay by holding BREADY HIGH. It asserts the write acknowledge signal WACK HIGH in the ACLK cycle following acceptance of a write response. WACK is asserted in AXI compatibility mode in addition to ACE configurations.

For interoperability of system components, ARM recommends that components interfacing with the ACE master are fully ACE compliant with no reliance on the subset of permitted BREADY and WACK behavior described for the processor.

Barriers

The processor does not send barrier transactions to the interconnect. All barriers are terminated within the cluster.

You must ensure that your interconnect and any peripherals connected to it do not return a write response for a transaction until that transaction would be considered complete by a later barrier. This means that the write must be observable to all other masters in the system. ARM expects the majority of peripherals to meet this requirement.

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