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You can configure the processor to use the CHI protocol for the master memory interface
Table A10-4 CHI channel properties
|Snoop acceptance capability||10||The SCU can accept and process a maximum of 10 snoop requests from the system.|
|DVM acceptance capability||4||
The SCU can accept and process a maximum of four DVM transactions from the system. Each of these four transactions can be a two part DVM message.
The interconnect must be configured to never send more than four DVM messages to a Cortex®‑A32 processor, otherwise the system might deadlock.
When there is a hit in L2 cache, the best case for response and data is 11 processor cycles. When there is a miss in L2 cache and a hit in L1 cache, the best case for response and data is 14 processor cycles.
Latencies can be higher if hazards occur or if there are not enough buffers to absorb requests.
|Miss||Best case six processor cycles when the SCU duplicate tags and L2 tags indicate the miss.|
The cluster takes a minimum of six cycles to provide a response to DVM packets.
|Snoop filter||Supported||The cluster provides support for an external snoop filter in an interconnect. It indicates when clean lines are evicted from the processor by sending Evict transactions on the CHI write channel. However, there are some cases where incorrect software can prevent an Evict transaction from being sent, therefore you must ensure that any external snoop filter is built to handle a capacity overflow that sends a back-invalidation to the processor if it runs out of storage.|
All transactions described by the CHI protocol: