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You can configure the processor to use the AXI protocol for the master memory interface.
The AXI master can delay accepting a read data channel transfer by holding RREADY LOW for an indeterminate number of cycles. RREADY can be deasserted LOW between read data channel transfers that form part of the same transaction.
The AXI master requires that the slave does not return a write response until it has received the write address.
The AXI master always accepts write responses without delay by holding BREADY HIGH.
You must ensure that your interconnect and any peripherals connected to it do not return a write response for a transaction until that transaction would be considered complete by a later barrier. This means that the write must be observable to all other masters in the system. ARM expects the majority of peripherals to meet this requirement.