A5.4 Disabling a cache

When the instruction cache is disabled:

  • Fetches cannot access any of the instruction cache arrays.
  • Instruction cache maintenance operations can still execute normally.
  • All instruction fetches to cacheable memory are treated as if they were non-cacheable. This means that instruction fetches might not be coherent with caches in other cores and software must take account of this.

When the data cache is disabled:

  • Load and store instructions do not access any of the L2 or L1 data cache arrays.
  • Data cache maintenance operations can still execute normally.
  • All load and store instructions to cacheable memory are treated as if they were non-cacheable. It means that they are not coherent with the caches in this core or the caches in other cores and software must take account of this.

You cannot disable the L2 and L1 data caches independently because the same enable bit controls them.

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