This chapter describes the CPU and SCU cache protection features of the Cortex®‑A32 processor.
A5.1 Cached memory types.
A5.2 Coherency between data caches with the MOESI
A5.3 Cache misses, unexpected cache hits, and speculative
A5.4 Disabling a cache.
A5.5 Invalidating or cleaning a cache.
A5.6 About read allocate mode.
A5.7 About cache protection.
A5.8 Error reporting.
A5.9 Error injection.