Part D Appendices

Table of Contents

A Signal Descriptions
A.1 About the signal descriptions
A.2 Processor configuration signals
A.3 Clock signals
A.4 Reset signals
A.5 GIC signals
A.6 Generic Timer signals
A.7 Power management signals
A.8 L2 error signals
A.9 ACP interface signals
A.10 Broadcast signals for the memory interface
A.11 AXI interface signals
A.12 ACE interface signals
A.13 CHI interface signals
A.14 Debug signals
A.15 APB interface signals
A.16 ATB interface signals
A.17 ETM signals
A.18 PMU interface signals
A.19 CTI interface signals
A.20 DFT interface signals
A.21 MBIST interface signals
B AArch32 UNPREDICTABLE Behaviors
B.1 Use of R15 by Instruction
B.2 UNPREDICTABLE instructions within an IT Block
B.3 Load/Store accesses crossing page boundaries
B.4 ARMv8 Debug UNPREDICTABLE behaviors
B.5 Other UNPREDICTABLE behaviors
C Revisions
C.1 Revisions
Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.