|Non-Confidential||PDF version||ARM 100241_0001_00_en|
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Some of the processor reset signals affect the debug registers.
Cold reset that covers reset of the processor logic and the integrated debug functionality.
The signal initializes the processor logic, including the debug, Embedded Trace Macrocell (ETM) trace unit, breakpoint, watchpoint logic, and performance monitors logic.
Warm reset that covers reset of the processor logic.
The signal resets some of the debug and performance monitor logic.
External debug reset that covers the resetting of the external debug interface and has no impact on the processor functionality.
The signal initializes the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.