C2.1 About the PMU

The processor includes performance monitors that enable you to gather various statistics on the operation of the processor and its memory system during runtime. They provide useful information that you can use when debugging or profiling code.

The PMU provides six counters. Each counter can count any of the events available in the processor. The absolute counts that the PMU records might vary because of pipeline effects. This variability only has an impact on the operation of the PMU when a counter is enabled for a short time.

Figure C2-1 PMU block diagram
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Event interface
Events from all other units from across the design are provided to the PMU.
System register and APB interface
You can program the PMU registers using the system registers or external APB interface.
The PMU has six 32-bit performance counters and one 64-bit cycle counter. The performance counters increment when they are enabled based on events.
PMU register interfaces
The processor supports access to the performance monitor registers from the internal system register interface or external debug interface.
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