C3.1 About the ETM

The ETM trace unit is a build-time configuration option. This module performs real-time instruction flow tracing that complies with the ETM architecture. As a CoreSight component, it is part of the ARM real-time debug solution.

Figure C3-1 ETM functional blocks
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Filtering and triggering resources

You can limit the amount of trace data that the ETM generates through filtering. For example, you can configure the ETM to generate trace only in a certain address range. More complicated filtering options, in the style of a logic analyzer, are also available.

The ETM trace unit can also generate a trigger signal to the Trace Capture Device to stop capturing trace.

Processor interface
Monitors the behavior of the processor and generates P0 elements that are executed instructions and exceptions that the ETM traces in program order.
Trace generation
Generates various trace packets that are based on P0 elements.
FIFO
The ETM generates trace in a highly compressed form. The FIFO can flatten trace bursts. When it becomes full, it signals overflow so that the trace generation logic does not generate any new trace until the FIFO becomes empty. The period without trace generation results in a gap in the trace in the debugger view.
Trace out
Trace from FIFO is output on the synchronous ATB interface.
Syncbridge
The ATB interface from the trace out block goes through an ATB synchronous bridge.
Interaction with the Performance Monitoring Unit (PMU)
The processor includes a PMU that enables counting events, such as cache misses, over a period. All PMU architectural events are available to the ETM trace unit through the extended input facility. The ETM trace unit uses four extended external input selectors to access the PMU events. Each selector can independently select one of the PMU events, which is then active for the cycles where the relevant events occur. Any ETM event register can access the selected event.

The processor supports only a memory-mapped interface to trace registers.

All trace register accesses through the external debug interface behave as if the processor power domain is powered down when debug double lock is set.

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