C3.2 Configuration options for the ETM unit and trace resources

The ETM unit is configurable. The processor implements options for the ETM unit and its resources.

Table C3-1 Configuration of trace generation

Description Configuration
Instruction address size in bytes 8
Data address size in bytes 0
Data value size in bytes 0
Virtual Machine ID size in bytes 1
Context ID size in bytes 4
Support for conditional instruction tracing Not implemented
Support for tracing of data Not implemented
Support for tracing of load and store instructions as P0 elements Not implemented
Support for cycle counting in the instruction trace Implemented
Support for branch broadcast tracing Implemented
Exception levels implemented in Non-secure state EL2, EL1, EL0
Exception levels implemented in Secure state EL3, EL1, EL0
Number of events supported in the trace 4
Return stack support Implemented
Tracing of SError exception support Implemented
Instruction trace cycle counting minimum threshold 1
Size of Trace ID 7 bits
Synchronization period support Read-write
Global timestamp size 64 bits
Number of cores available for tracing 1
ATB trigger support Implemented
Low-power behavior override Implemented
Stall control support Implemented
Support for no overflows in the trace Not implemented

Table C3-2 Configuration of trace resources

Description Configuration
Number of resource selection pairs implemented 8
Number of external input selectors implemented 4
Number of external inputs implemented 30, 4 CTI + 26 PMU
Number of counters implemented 2
Reduced function counter implemented Not implemented
Number of sequencer states implemented 4
Number of Virtual Machine ID comparators implemented 1
Number of Context ID comparators implemented 1
Number of address comparator pairs implemented 4
Number of single-shot comparator controls 1
Number of processor comparator inputs implemented 0
Data address comparisons implemented Not implemented
Number of data value comparators implemented 0
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