B1.3 c1 registers

The processor can access different 32-bit wide system registers. Registers where CRn has the value one are called c1 registers.

The following table shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c1.

Table B1-3 c1 register summary

Op1 CRm Op2 Name Reset Description
0 c0 0 SCTLR 0x00C50838

B1.105 System Control Register

The reset value depends on inputs, CFGTE, CFGEND, and VINITHI. The value listed here assumes these signals are set to LOW.

1 ACTLR

0x00000000

B1.32 Auxiliary Control Register

2 CPACR 0x00000000

B1.41 Architectural Feature Access Control Register

c1 0 SCR 0x00000000

B1.104 Secure Configuration Register

1 SDER 0x00000000

B1.107 Secure Debug Enable Register

2 NSACR

0x00000000

B1.98 Non-Secure Access Control Register

c3 1 SDCR 0x00000000 B1.106 Secure Debug Control Register
4 c0 0 HSCTLR 0x03C50838

B1.67 Hyp System Control Register

1 HACTLR 0x00000000 B1.55 Hyp Auxiliary Control Register
c1 0 HCR 0x00000000

B1.61 Hyp Configuration Register

1 HDCR 0x00000006

B1.63 Hyp Debug Control Register

2 HCPTR 0x000033FF

B1.60 Hyp Architectural Feature Trap Register

The reset value depends on the FPU and NEON configuration. If Advanced SIMD and floating-point are implemented, the reset value is 0x000033FF. If Advanced SIMD and floating-point are not implemented, the reset value is 0x0000BFFF.

3 HSTR 0x00000000

B1.69 Hyp System Trap Register

4 HCR2 0x00000000 B1.62 Hyp Configuration Register 2
7 HACR 0x00000000 B1.54 Hyp Auxiliary Configuration Register
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