B1.20 AArch32 Identification registers

The following table shows the identification registers.

Table B1-19 Identification registers

Name CRn Op1 CRm Op2 Reset Description
MIDR c0 0 c0 0 0x410FD011

B1.96 Main ID Register

CTR 1 0x84448004

B1.46 Cache Type Register

TCMTR 2 0x00000000

B1.108 TCM Type Register

TLBTR 3 0x00000000

B1.109 TLB Type Register


B1.97 Multiprocessor Affinity Register

The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the device implements.

REVIDR 6 0x00000000 B1.102 Revision ID Register
ID_PFR0 c1 0 0x00000131

B1.84 Processor Feature Register 0

ID_PFR1 1 0x10011011

B1.85 Processor Feature Register 1

Bits [31:28] are 0x1 if the GIC CPU interface is implemented and enabled, and 0x0 otherwise.

ID_DFR0 2 0x03010066

B1.73 Debug Feature Register 0

Bits [19:16] are 0x1 if ETM is implemented, and 0x0 otherwise.

ID_AFR0 3 0x00000000 B1.72 Auxiliary Feature Register 0
ID_MMFR0 4 0x10201105

B1.80 Memory Model Feature Register 0

ID_MMFR1 5 0x40000000

B1.81 Memory Model Feature Register 1

ID_MMFR2 6 0x01260000

B1.82 Memory Model Feature Register 2

ID_MMFR3 7 0x02102211

B1.83 Memory Model Feature Register 3

ID_ISAR0 c2 0 0x02101110

B1.74 Instruction Set Attribute Register 0

ID_ISAR1 1 0x13112111

B1.75 Instruction Set Attribute Register 1

ID_ISAR2 2 0x21232042

B1.76 Instruction Set Attribute Register 2

ID_ISAR3 3 0x01112131

B1.77 Instruction Set Attribute Register 3

ID_ISAR4 4 0x00011142

B1.78 Instruction Set Attribute Register 4

ID_ISAR5 c0 0 c2 5 0x00011121

B1.79 Instruction Set Attribute Register 5

ID_ISAR5 has the value 0x00010001 if the Cryptographic Extension is not implemented and enabled.

CCSIDR 1 c0 0 -

B1.39 Cache Size ID Register

CLIDR 1 0x0A200023

B1.40 Cache Level ID Register

The value is 0x09200003 if the L2 cache is not implemented.

AIDR 7 0x00000000

B1.34 Auxiliary ID Register

CSSELR 2 c0 0 0x00000000 B1.45 Cache Size Selection Register
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