B1.22 AArch32 Fault handling registers

The following table shows the Fault handling registers in the AArch32 Execution state.

Table B1-21 Fault handling registers

Name CRn Op1 CRm Op2 Reset Description
DFSR c5 0 c0 0 UNK B1.49 Data Fault Status Register
IFSR 1 UNK B1.87 Instruction Fault Status Register
ADFSR c1 0 0x00000000 B1.33 Auxiliary Data Fault Status Register
AIFSR 1 0x00000000 B1.35 Auxiliary Instruction Fault Status Register
DFAR c6 0 c0 0 UNK

Data Fault Address Register, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile

IFAR 2 UNK

Instruction Fault Address Register, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile

The Virtualization registers include additional fault handling registers. See B1.28 AArch32 Virtualization registers for more information.

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