B1.26 AArch32 Performance monitor registers

The following table shows the performance monitor registers.

See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table B1-25 Performance monitor registers

Name CRn Op1 CRm Op2 Reset Description
PMCR c9 0 c12 0 0x41063000 C9.2 Performance Monitors Control Register
PMCNTENSET 1 UNK

Performance Monitors Count Enable Set Register

PMCNTENCLR 2 UNK

Performance Monitors Count Enable Clear Register

PMOVSR 3 UNK

Performance Monitors Overflow Flag Status Register

PMSWINC 4 UNK

Performance Monitors Software Increment Register

PMSELR 5 UNK

Performance Monitors Event Counter Selection Register

PMCEID0 6 0x6FFFBFFF

C9.3 Performance Monitors Common Event Identification Register 0

The reset value is 0x6E3FBFFF if L2 cache is not implemented.

PMCEID1 7 0x00000000 C9.4 Performance Monitors Common Event Identification Register 1
PMCCNTR c13 0 UNK

Performance Monitors Cycle Count Register

PMXEVTYPER 1 UNK Performance Monitors Selected Event Type Register
PMXEVCNTR 2 UNK

Performance Monitors Event Count Registers

PMUSERENR c14 0 0x00000000

Performance Monitors User Enable Register

PMINTENSET 1 UNK

Performance Monitors Interrupt Enable Set Register

PMINTENCLR 2 UNK Performance Monitors Interrupt Enable Clear Register
PMOVSSET 3 UNK

Performance Monitor Overflow Flag Status Set Register

PMEVCNTR0 c14 0 c8 0 UNK

Performance Monitors Event Count Register 0

PMEVCNTR1 1 UNK  
PMEVCNTR2 2 UNK  
PMEVCNTR3 3 UNK  
PMEVCNTR4 4 UNK  
PMEVCNTR5 5 UNK  
PMEVTYPER0 c12 0 UNK Performance Monitors Selected Event Type Register 0
PMEVTYPER1 1 UNK  
PMEVTYPER2 2 UNK  
PMEVTYPER3 3 UNK  
PMEVTYPER4 4 UNK  
PMEVTYPER5 5 UNK  
PMCCFILTR c15 7 0x00000000 Performance Monitors Cycle Count Filter Register
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