B1.27 AArch32 Secure registers

The following table shows the Secure registers.

See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table B1-26 Security registers

Name CRn Op1 CRm Op2 Reset Description
SCR c1 0 c1 0 0x00000000 B1.104 Secure Configuration Register
SDER 1 UNK Secure Debug Enable Register
NSACR 2

0x00000000

B1.98 Non-Secure Access Control Register

VBAR c12 0 c0 0

0x00000000

B1.119 Vector Base Address Register

0x00000000 is the secure reset value and UNK is the non-secure reset value.

MVBAR 1 UNK

Monitor Vector Base Address Register

ISR c1 0 UNK

Interrupt Status Register

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