B1.31 AArch32 Implementation defined registers

Implementation defined registers provide test features and any required configuration options specific to the Cortex®‑A32 processor.

The following table shows the 32-bit wide implementation defined registers.

Table B1-29 Memory access registers

Name CRn Op1 CRm Op2 Reset Width Description
L2CTLR c9 1 c0 2 - 32-bit

B1.92 L2 Control Register

The reset value depends on the processor configuration.

L2ECTLR 3 0x00000000 32-bit B1.93 L2 Extended Control Register
L2ACTLR c15 1 c0 0 0x80000000 32-bit

B1.91 L2 Auxiliary Control Register

This is the reset value for an ACE interface. For an AXI interface the reset value is 0x80000008. For a CHI interface the reset value is 0x80004008.

CBAR c3 0 - 32-bit

B1.38 Configuration Base Address Register

The reset value depends on the processor configuration.

CDBGDR0 3 c0 0 UNK 32-bit

Data Register 0, see C5.1 About direct access to internal memory for information on how these registers are used.

CDBGDR1 1 UNK 32-bit Data Register 1, see C5.1 About direct access to internal memory
CDBGDR2 2 UNK 32-bit Data Register 2, see C5.1 About direct access to internal memory
CDBGDR3 3 UNK 32-bit Data Register 3, see C5.1 About direct access to internal memory.
CDBGDCT c2 0 UNK 32-bit Data Cache Tag Read Operation Register, see C5.1 About direct access to internal memory
CDBGICT 1 UNK 32-bit Instruction Cache Tag Read Operation Register, see C5.1 About direct access to internal memory
CDBGDCD c4 0 UNK 32-bit Data Cache Data Read Operation Register, see C5.1 About direct access to internal memory
CDBGICD 1 UNK 32-bit Instruction Cache Data Read Operation Register, see C5.1 About direct access to internal memory
CDBGTD 2 UNK 32-bit TLB Data Read Operation Register, see C5.1 About direct access to internal memory
CPUACTLR - 0 c15 - 0x00000000090CA000 64-bit B1.42 CPU Auxiliary Control Register
CPUECTLR - 1 c15 - 0x0000000000000000 64-bit B1.43 CPU Extended Control Register
CPUMERRSR - 2 c15 - - 64-bit B1.44 CPU Memory Error Syndrome Register
L2MERRSR - 3 c15 - - 64-bit B1.94 L2 Memory Error Syndrome Register
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