B1.96 Main ID Register

The MIDR characteristics are:

Purpose
Provides identification information for the processor, including an implementer code for the device and a device ID number.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO
Configurations

MIDR is architecturally mapped to the external register MIDR_EL1.

Attributes
MIDR is a 32-bit register.
Figure B1-50 MIDR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Implementer, [31:24]

Indicates the implementer code. This value is:

0x41ARM.
Variant, [23:20]

Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status. This value is:

0x0r0p1.
Architecture, [19:16]

Indicates the architecture code. This value is:

0xFDefined in the CPUID scheme.
PartNum, [15:4]

Indicates the primary part number. This value is:

0xD01Cortex®‑A32 processor.
Revision, [3:0]

Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status. This value is:

0x1r0p1.

To access the MIDR:

MRC p15, 0, <Rt>, c0, c0, 0; Read MIDR into Rt

Register access is encoded as follows:

Table B1-81 MIDR access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0000 000

The MIDR can be accessed through the external debug interface, offset 0xD00.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.