B1.84 Processor Feature Register 0

The ID_PFR0 characteristics are:

Purpose
Gives top-level information about the instruction sets supported by the processor in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

ID_PFR0 must be interpreted with ID_PFR1.

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_PFR0 is a 32-bit register.
Figure B1-39 ID_PFR0 bit assignments
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[31:16]

Reserved, res0.

State3, [15:12]

Indicates support for Thumb Execution Environment (T32EE) instruction set. This value is:

0x0Processor does not support the T32EE instruction set.
State2, [11:8]

Indicates support for Jazelle. This value is:

0x1Processor supports trivial implementation of Jazelle.
State1, [7:4]

Indicates support for T32 instruction set. This value is:

0x3Processor supports T32 encoding after the introduction of Thumb-2 technology, and for all 16-bit and 32-bit T32 basic instructions.
State0, [3:0]

Indicates support for A32 instruction set. This value is:

0x1A32 instruction set implemented.

To access the ID_PFR0:

MRC p15,0,<Rt>,c0,c1,0 ; Read ID_PFR0 into Rt

Register access is encoded as follows:

Table B1-67 ID_PFR0 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0001 000
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