B1.85 Processor Feature Register 1

The ID_PFR1 characteristics are:

Purpose
Provides information about the programmers model and architecture extensions supported by the processor.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with ID_PFR0.

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_PFR1 is a 32-bit register.
Figure B1-40 ID_PFR1 bit assignments
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GIC CPU, [31:28]

GIC CPU support:

0x0GIC CPU interface is disabled, GICCDISABLE is HIGH, or not implemented.
0x1GIC CPU interface is implemented and enabled, GICCDISABLE is LOW.
[27:20]
Reserved, RAZ.
GenTimer, [19:16]

Generic Timer support:

0x1Generic Timer implemented.
Virtualization, [15:12]

Indicates support for Virtualization:

0x1Virtualization implemented.
MProgMod, [11:8]

M profile programmers model support:

0x0Not supported.
Security, [7:4]

Security support:

0x1Security implemented. This includes support for Monitor mode and the SMC instruction.
ProgMod, [3:0]

Indicates support for the standard programmers model for ARMv4 and later.

Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined and System modes:

0x1Supported.

To access the ID_PFR1:

MRC p15,0,<Rt>,c0,c1,1 ; Read ID_PFR1 into Rt

Register access is encoded as follows:

Table B1-68 ID_PFR1 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0001 001
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