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The ID_PFR1 characteristics are:
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
Must be interpreted with ID_PFR0.
There is one copy of this register that is used in both Secure and Non-secure states.
GIC CPU support:
|GIC CPU interface is disabled, GICCDISABLE is HIGH, or not implemented.|
|GIC CPU interface is implemented and enabled, GICCDISABLE is LOW.|
Generic Timer support:
|Generic Timer implemented.|
Indicates support for Virtualization:
M profile programmers model support:
|Security implemented. This includes support for Monitor mode and the SMC instruction.|
Indicates support for the standard programmers model for ARMv4 and later.
Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined and System modes:
To access the ID_PFR1:
MRC p15,0,<Rt>,c0,c1,1 ; Read ID_PFR1 into Rt
Register access is encoded as follows:
Table B1-68 ID_PFR1 access encoding