B1.73 Debug Feature Register 0

The ID_DFR0 characteristics are:

Purpose
Provides top level information about the debug system in AArch32.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

Must be interpreted with the Main ID Register, MIDR.

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
ID_DFR0 is a 32-bit register.
Figure B1-28 ID_DFR0 bit assignments
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[31:28]

Reserved, res0.

PerfMon, [27:24]

Indicates support for performance monitor model:

0x3Support for Performance Monitor Unit version 3 (PMUv3) system registers.
MProfDbg, [23:20]

Indicates support for memory-mapped debug model for M profile processors:

0x0Processor does not support M profile Debug architecture.
MMapTrc, [19:16]

Indicates support for memory-mapped trace model:

0x0ETM is not implemented.
0x1Support for ARM trace architecture, with memory-mapped access.

In the Trace registers, the ETMIDR gives more information about the implementation.

CopTrc, [15:12]

Indicates support for coprocessor-based trace model:

0x0Processor does not support ARM trace architecture, with CP14 access.
[11:8]
Reserved, RAZ.
CopSDbg, [7:4]

Indicates support for coprocessor-based Secure debug model:

0x6Processor supports v8 Debug architecture, with CP14 access.
CopDbg, [3:0]

Indicates support for coprocessor-based debug model:

0x6Processor supports v8 Debug architecture, with CP14 access.

To access the ID_DFR0:

MRC p15,0,<Rt>,c0,c1,2 ; Read ID_DFR0 into Rt

Register access is encoded as follows:

Table B1-56 ID_DFR0 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0001 010
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